Integrated circuit (IC) chips are becoming increasingly complex, such that Systems on a Chip (SoC's) are becoming more commonplace. SoC's comprise multiple independently designed logic functions combined on a single chip to perform complex operations. The independently developed logic circuits each have an independently designed clock domain, the frequency thereof being optimized to meet particular performance criteria. Each circuit is designed as a general macro without a priori knowledge of final chip packaging, which presents a challenge for logic built-in self-testing (LBIST) of the IC package. Currently, LBIST for such SoC's involves independent testing of each clock domain, requiring detailed a priori knowledge of the clock domain frequency requirements as well as additional test design overhead to achieve desired results. An even further challenge is presented by logic self-testing of multiple chips on a card.
Accordingly, it is desirable to provide a robust logic built-in self-test (LBIST) structure that applies to an aggregation of independently developed circuits, without requiring a priori knowledge of independent clock domain requirements. It is further desirable that such a LBIST structure be applicable to testing multiple chips in a system, without sacrificing repeatable chip signatures.